Q44 ECS Solid State Letters, 4 (9) Q44-Q46 (2015) 2162-8742/2015/4(9)/Q44/3/$33.00 © The Electrochemical Society Effects of Thermal Annealing on La2O3 Gate Dielectric of InGaZnO Thin-Film Transistor

The effects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor (TFT) are investigated by varying annealing temperature. Due to densification and enhanced moisture resistance of the La2O3 film, its surface roughness and interface with InGaZnO are improved by the thermal annealing, thus leading to significant improvement in the TFT electrical performance. However, higher-temperature (450◦C) annealing deteriorates the dielectric roughness and induces more traps associated with grain boundaries in the La2O3 film. The TFT with an appropriate annealing (350◦C) shows the best performance with smallest sub-threshold swing (0.276 V/dec), lowest threshold voltage (3.01 V), highest field-effect mobility (23.2 cm2/V.s) and largest on-off current ratio (3.52 × 108)