the niti e b tion for decreasing the total global interconnect length that can lim-it IC performance. It refers to multiple conv chips/wafers may be stacked vertically an nected [1]. Based on current research and has the potential to dramatically enhance c ty in i s (ME ey tech e perfo nding, ximize physical properties such as low dielectric constant, low moisture absorption, low cure temperature, high degree of planarization, low level of ionic contaminants, high optical clarity, good thermal stability, excellent chemical resistance, and good compatibility with various metallization systems [4,5]. The monomer structure of BCB is shown in Fig. 1 [6]. In this research, we investigated the process optimization and studied the bonding mechanis...
The deposition rate, the etch rate in a HF-based solution and the residual internal stress of PECVD ...
The presented fabrication technology enables the direct integration of electrical interconnects duri...
To bridge the technology gap between IC-level and board-level fabrications, a fully additive selecti...
3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered...
Bonding wafers prior to a wet etching step is a desirable yet complex process step. The use of the p...
Itigh strength bonds can be formed between portions of silicon wafer coated with reflowed BPSG at te...
In this publication the challenges of bonding InP and BiCMOS wafers with high topology are described...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
In this paper, intermediate layer bonding technologies using SU-8 and BCB are successfully demonstra...
Die-to-wafer (D2W) heterogeneous integration using thermal compression bonding (TCB) faces a serious...
The solder is the one of the most interconnect joining material in the denser electronic interconnec...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 20...
Presented is a novel process of benzo-cyclo-butene (BCB) bonding for a wafer level package with stam...
Thin film polymers play an essential role in system integration. The curing temperature and the mech...
A novel wafer bonding technology, designed to enable covalent and conductive wafer bonding processes...
The deposition rate, the etch rate in a HF-based solution and the residual internal stress of PECVD ...
The presented fabrication technology enables the direct integration of electrical interconnects duri...
To bridge the technology gap between IC-level and board-level fabrications, a fully additive selecti...
3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered...
Bonding wafers prior to a wet etching step is a desirable yet complex process step. The use of the p...
Itigh strength bonds can be formed between portions of silicon wafer coated with reflowed BPSG at te...
In this publication the challenges of bonding InP and BiCMOS wafers with high topology are described...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
In this paper, intermediate layer bonding technologies using SU-8 and BCB are successfully demonstra...
Die-to-wafer (D2W) heterogeneous integration using thermal compression bonding (TCB) faces a serious...
The solder is the one of the most interconnect joining material in the denser electronic interconnec...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 20...
Presented is a novel process of benzo-cyclo-butene (BCB) bonding for a wafer level package with stam...
Thin film polymers play an essential role in system integration. The curing temperature and the mech...
A novel wafer bonding technology, designed to enable covalent and conductive wafer bonding processes...
The deposition rate, the etch rate in a HF-based solution and the residual internal stress of PECVD ...
The presented fabrication technology enables the direct integration of electrical interconnects duri...
To bridge the technology gap between IC-level and board-level fabrications, a fully additive selecti...