LBDR: An efficient unicast routing support for

The roadmap for high-performance computing it is currently switching to multi-core architectures. Industry has shifted to the multi-core paradigm as single-core processors are reaching the power consumption wall. The solution is to put multiple and simple processors in the same chip fabric becoming chip multiprocessors (CMPs). An efficient interconnect layer for CMP archi-tectures is needed to connect all the cores. Networks-on-chip (NoCs) are the key components of these architectures, and they have to deal with the com-munication scalability challenge while meeting tight power, area and latency design constraints. 2D mesh topologies are usually preferred by designers of general purpose NoCs. However, manufacturing faults may break their regularity. Moreover, resource management frameworks may require the segmentation of the net-work into irregular regions under virtualization or power-awareness scenarios. Under these conditions, efficient routing becomes a challenge. Although o