Effect of Threshold-Voltage Instability on SiC Power MOSFET High-Temperature Reliability

The gate-bias stress-induced threshold-voltage instability observed in lateral SiC MOSFETs is also present in fully processed SiC DMOSFETs, and the shifts are comparable in magnitude, and similar in their response to bias-stress time, gate-oxide field, and temperature (1). Therefore, it is highly likely that the same near-interfacial oxide trapping mechanisms are the cause of the observed instability in both the ID-VGS and ID-VDS characteristics of SiC power MOSFETs. Bias stressing, while also allowing the rated current to flow through the channel of the power MOSFET, results in an increase in the threshold voltage (VT) instability effect compared to gate-bias stressing alone. Although the effect of this ON-state stressing is only slightly worse when measured at high-current levels on