Add to ORKGWe propose an algorithm for ihe design of multiple-valued current-mode CMOS logic (CMCL) circuiis that i s based on the cost-fable iechnique. The a1 orithm is a heuristic search technique AO ' algorithm) L O, l l] ap-Exhaustive Search while providing realizations that are almost as good. A new cost-table is also proposed ihai results in better realizations ihan obtained with a previ-ous cost-table [ Id].
The paper presents the concepts of pseudoprime and modulo correlativity and establishes the relation...
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued lo...
Use of current-mode CMOS circuits for implementation of multiple-valued logic (MVL) functions has be...
We propose an algorithm for ihe design of multiple-valued current-mode CMOS logic (CMCL) circuiis th...
Abstract—We analyze the computational complexity of the cost-table approach to designing multiple-va...
Over the last two decades, design using Multiple-Valued Logic (MVL) has been receiving considerable ...
This thesis presents a self-restored current-mode CMOS multiple-valued logic (MVL) design architectu...
Over the past two decades, researchers have proposed a variety of circuits to implement Multiple-Val...
This paper considers the applicability of multiple-valued logic (MVL) circuits in implementation of ...
Complexity analysis of the cost-table approach to the design of multiple-valued logic circuit
Abstruct- We propose a heuristic for finding minimal cost-tables for use in the design of multiple-v...
Abstract: The thesis describes the design and implementation of a carry save adder cell for multi-va...
This thesis describes the design and implementation of a carry save adder cell for multivalued logic...
The development of modern integration technologies is normally driven by the needs of digital CMOS c...
Multiple-valued logic (MVL) circuits can be designed and implemented, utilizing 4 levels of logic, i...
The paper presents the concepts of pseudoprime and modulo correlativity and establishes the relation...
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued lo...
Use of current-mode CMOS circuits for implementation of multiple-valued logic (MVL) functions has be...
We propose an algorithm for ihe design of multiple-valued current-mode CMOS logic (CMCL) circuiis th...
Abstract—We analyze the computational complexity of the cost-table approach to designing multiple-va...
Over the last two decades, design using Multiple-Valued Logic (MVL) has been receiving considerable ...
This thesis presents a self-restored current-mode CMOS multiple-valued logic (MVL) design architectu...
Over the past two decades, researchers have proposed a variety of circuits to implement Multiple-Val...
This paper considers the applicability of multiple-valued logic (MVL) circuits in implementation of ...
Complexity analysis of the cost-table approach to the design of multiple-valued logic circuit
Abstruct- We propose a heuristic for finding minimal cost-tables for use in the design of multiple-v...
Abstract: The thesis describes the design and implementation of a carry save adder cell for multi-va...
This thesis describes the design and implementation of a carry save adder cell for multivalued logic...
The development of modern integration technologies is normally driven by the needs of digital CMOS c...
Multiple-valued logic (MVL) circuits can be designed and implemented, utilizing 4 levels of logic, i...
The paper presents the concepts of pseudoprime and modulo correlativity and establishes the relation...
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued lo...
Use of current-mode CMOS circuits for implementation of multiple-valued logic (MVL) functions has be...