The Effect of IEC-Like Fast Transients on RC-Triggered ESD Power Clamps

Abstract—Four power-rail electrostatic-discharge (ESD) clamp circuits with different ESD-transient detection circuits have been fabricated in a 0.18-μm CMOS process to investigate their sus-ceptibility against electrical fast-transient (EFT) tests. Under EFT tests, where the integrated circuits in a microelectronic system have been powered up, the feedback loop used in the power-rail ESD clamp circuits may lock the ESD-clamping NMOS in a “latch-on ” state. Such a latch-on ESD-clamping NMOS will con-duct a huge current between the power lines to perform a latchup-like failure after EFT tests. A modified power-rail ESD clamp circuit has been proposed to solve this latchuplike failure and to provide a high-enough chip-level ESD robustness. Index Terms—Electrical fast-transient (EFT) test, electromag-netic compatibility, electrostatic discharge (ESD), ESD protection circuit, latchup, system-level ESD stress. I