This paper first presents the requirements for and the architectural framework of a type of real-time parallel dataflow computer architecture, specifically, a Hybrid Data/Command Driven Architecture (HDCA). Application of such an architecture is discussed. Goals, strategies, and algorithms for both static load-balancing and dynamic resource allocation on an HDCA system are presented. A parallel simulation of an HDCA system employing the presented static load-balancing and dynamic resource allocation algorithms is developed and presented. The parallel simulation was executed on a parallel computer system for increased fidelity. Analysis of simulation results for two example applications of the architecture allowed verification of design goal...
Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing p...
The information processing is in continuous progress. High Performance Computing is now a trend. The...
Our goal is to devise a computer comprising large numbers of cooperating processors (LSI). In doing ...
A single-chip, hybrid, heterogeneous, and dynamic shared memory multiprocessor architecture is being...
This paper describes the evolution of dataflow computers from the first static design to the newest ...
Parallel Processing: CONPAR 92-VAPP VWe propose execution control scheme to realize an efficient mul...
The primary objective of the proposed research is to define and evaluate an architecture for a compu...
Dataflow architectures offer the ability to trade program level parallelism in order to overcome mac...
This paper describes about Data Flow Computers. The dataflow model of computation offers an attracti...
The dataflow model of computation offers a powerful alternative to the von Neumann based model for e...
Dataflow may be thought of as a language-oriented approach to the design and organization of computi...
Functional dataflow programming languages are designed to create parallel portable programs. The sou...
In this thesis, we show how challenges in parallel and distributed systems can be overcome for speci...
In recent years, sweeping changes in computer architecture have been transpiring as the technology c...
Reconfigurable and dynamic computer architecture is an exciting area of research that is rapidly exp...
Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing p...
The information processing is in continuous progress. High Performance Computing is now a trend. The...
Our goal is to devise a computer comprising large numbers of cooperating processors (LSI). In doing ...
A single-chip, hybrid, heterogeneous, and dynamic shared memory multiprocessor architecture is being...
This paper describes the evolution of dataflow computers from the first static design to the newest ...
Parallel Processing: CONPAR 92-VAPP VWe propose execution control scheme to realize an efficient mul...
The primary objective of the proposed research is to define and evaluate an architecture for a compu...
Dataflow architectures offer the ability to trade program level parallelism in order to overcome mac...
This paper describes about Data Flow Computers. The dataflow model of computation offers an attracti...
The dataflow model of computation offers a powerful alternative to the von Neumann based model for e...
Dataflow may be thought of as a language-oriented approach to the design and organization of computi...
Functional dataflow programming languages are designed to create parallel portable programs. The sou...
In this thesis, we show how challenges in parallel and distributed systems can be overcome for speci...
In recent years, sweeping changes in computer architecture have been transpiring as the technology c...
Reconfigurable and dynamic computer architecture is an exciting area of research that is rapidly exp...
Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing p...
The information processing is in continuous progress. High Performance Computing is now a trend. The...
Our goal is to devise a computer comprising large numbers of cooperating processors (LSI). In doing ...