In Proceedings of 7th IEEE Int’l Conf. on Wafer Scale Integration pp.238-247 Jan.1995 A Cache Coherency Protocol for Multiprocessor Chip

A bus connected multiprocessor is one of the most promising types of small scale parallel machines because of its simple and economical structure. Usually, all processors share a common address space of the shared memory. In order to reduce the access latency and the bus congestion, each processor provides a private cache with a snoop mechanism[1]