Cache Coherence for GPU Architectures

While scalable coherence has been extensively stud-ied in the context of general purpose chip multiprocessors (CMPs), GPU architectures present a new set of challenges. Introducing conventional directory protocols adds unneces-sary coherence traffic overhead to existing GPU applica-tions. Moreover, these protocols increase the verification complexity of the GPU memory system. Recent research, Library Cache Coherence (LCC) [34, 54], explored the use of time-based approaches in CMP coherence protocols. This paper describes a time-based coherence framework for GPUs, called Temporal Coherence (TC), that exploits globally synchronized counters in single-chip systems to de-velop a streamlined GPU coherence protocol. Synchronized counters enable all coherence transitions, such as invali-dation of cache blocks, to happen synchronously, eliminat-ing all coherence traffic and protocol races. We present an implementation of TC, called TC-Weak, which eliminates LCC’s trade-off between stalling stores and increasing L1 miss rates to improve performance and reduce interconnect traffic. By providing coherent L1 caches, TC-Weak improves the performance of GPU applications with inter-workgroup communication by 85 % over disabling the non-coherent L1 caches in the baseline GPU. We also find that write-through protocols outperform a writeback protocol on a GPU as the latter suffers from increased traffic due to unnecessary re-fills of write-once data.