textThe advancements of semiconductor processing technology have led to the ability for computing platforms to operate on large amounts of data at very high clock speeds. To fully utilize this processing power the components must have data continually available for operation upon and transport to other system components. To enable this data requirement, high speed serial links have replaced slower parallel communication protocols. Serial interfaces inherently require fewer signals for communication and thus reduce the device pin count, area and cost. A serial communication interface can also be run at a higher frequency because the clock skew between channels is no longer an issue since the data transmitted on various channels is independen...
Channel bandwidth and manufacturing process have become two limitations in today\u27s high speed des...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
This thesis consists of a 28 nm submicron circuit design for high speed transceiver circuits used in...
This thesis describes the modeling and simulation of 10 Gb/s serial data link architectures. The fir...
This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS ...
High-speed wireline transceivers are analog/mixed-signal electronic circuits in charge of transferri...
In this paper, the equalization techniques for highspeed interconnect transceivers are discussed. Se...
The IEEE 802.3aq standard recommends a multi-tap decision feedback equalizer be implemented to remov...
Project (M.S., Computer Engineering)--California State University, Sacramento, 2014.High speed seria...
The growth in worldwide network traffic due to the rise of cloud computing and wireless video consumpt...
High-speed serial input-output (I/O) link has required advanced equalization and modulation techniqu...
This dissertation develops an unclocked receiver analog decision-feedback equalizer (ADFE) circuit a...
Increasing data rates over electrical channels with significant frequency-dependent loss is difficul...
Channel impairments in high data rates make Analog-to-digital (ADC) serial link a very attractive ch...
This paper presents a parallel implementation technique of digital equalizer for high-speed wireline...
Channel bandwidth and manufacturing process have become two limitations in today\u27s high speed des...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
This thesis consists of a 28 nm submicron circuit design for high speed transceiver circuits used in...
This thesis describes the modeling and simulation of 10 Gb/s serial data link architectures. The fir...
This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS ...
High-speed wireline transceivers are analog/mixed-signal electronic circuits in charge of transferri...
In this paper, the equalization techniques for highspeed interconnect transceivers are discussed. Se...
The IEEE 802.3aq standard recommends a multi-tap decision feedback equalizer be implemented to remov...
Project (M.S., Computer Engineering)--California State University, Sacramento, 2014.High speed seria...
The growth in worldwide network traffic due to the rise of cloud computing and wireless video consumpt...
High-speed serial input-output (I/O) link has required advanced equalization and modulation techniqu...
This dissertation develops an unclocked receiver analog decision-feedback equalizer (ADFE) circuit a...
Increasing data rates over electrical channels with significant frequency-dependent loss is difficul...
Channel impairments in high data rates make Analog-to-digital (ADC) serial link a very attractive ch...
This paper presents a parallel implementation technique of digital equalizer for high-speed wireline...
Channel bandwidth and manufacturing process have become two limitations in today\u27s high speed des...
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
This thesis consists of a 28 nm submicron circuit design for high speed transceiver circuits used in...