Digitally assisted test methodology for RF receivers

textAddressing the high cost of RF instrumentation has motivated significant research activity, where researchers have proposed various non-standard and alternative test methods of RF circuits to mitigate high test cost. This dissertation describes a test methodology for RF receivers, whereby simple digital circuits comprise the core of the otherwise complex and costly broadband RF/analog signal generation. The proposed test methodology relies on a digital clock, commonly available to RF ICs for the purpose of digital communication, to generate the broadband RF stimulus needed for the receiver analog tests. The test method also utilizes commonly available baseband signal digitization (on-chip or off-chip) to acquire the baseband signal. It then relies on sophisticated, but inexpensive, signal processing to extract and compute standard RF performance parameters, like gain, noise figure (NF), and input-referred third-order intercept point (IIP3). In addition, the test method can extract important baseband (BB) parameters like the BB filter 3 dB bandwidth (BW), filter rejection at specific BB frequencies, or the BB filter profile. The motivation behind the proposed test methodology can be categorized as both architectural and cost reduction-oriented. Architecturally, the proposed test method aims at shifting the complexity involved in the test of RF receivers from the hardware (input) RF signal generation side to the signal processing done on the (output) baseband side. The process of shifting the complexity from the hardware design side to the signal processing side involves significant complex and sophisticated analysis, which is part of this dissertation. Cost-wise, the proposed test methodology enables the use of digital automatic test equipment (ATE) with limited baseband capability, instead of the full standard RF testers. Such a step reduces the initial tester cost and impacts the cost/sec figure spent on test for the life of the ATE tester, thus leading to test cost reduction.Electrical and Computer Engineerin