This paper presents a new approach that allows remote testing and diagnosis of complex (Systems-on-Chip) and embedded IP cores. The approach extends both on-chip design-for-test (DFT) architectures and network management protocols to take full benefits from existing networking infrastructures. By running intensive experimentation on ITC’99 and ITC'02 design benchmarks, the efficiency of the proposed testing and diagnosis methodology is analyzed.
Design simpli¯cation is becoming necessary to respect the target time-to-market of SoCs, and this go...
Spurred by technology leading to the availability of millions of gates per chip, system-level integr...
This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network ...
Abstract—Lifetime concerns for complex systems-on-a-chip (SoC) designs due to decreasing levels in r...
Due to recent progress in semiconductor technology, communication is becoming the major source of ex...
System-on-a-chip (SoC) and reuse of intellectual property (IP) is the emerging paradigm for integrat...
This thesis presented a new method for testing routers and cores on Network-On-Chip (NoC) systems.It...
Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SO...
Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dep...
This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of N...
Abstract—Network-on-chip (NoC) communication fabrics will be increasingly used in many large multico...
Periodic on-chip scan-based tests have to be applied to a many-core processor to improve its dependa...
International audienceThis paper concerns the local and remote use of an Integrated Circuits (IC) Au...
Increasing demand for high quality and reliable operation of the telecommunication network services ...
In this paper, a hardware design of digital systems with remote-diagnostic capability is presented. ...
Design simpli¯cation is becoming necessary to respect the target time-to-market of SoCs, and this go...
Spurred by technology leading to the availability of millions of gates per chip, system-level integr...
This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network ...
Abstract—Lifetime concerns for complex systems-on-a-chip (SoC) designs due to decreasing levels in r...
Due to recent progress in semiconductor technology, communication is becoming the major source of ex...
System-on-a-chip (SoC) and reuse of intellectual property (IP) is the emerging paradigm for integrat...
This thesis presented a new method for testing routers and cores on Network-On-Chip (NoC) systems.It...
Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SO...
Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dep...
This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of N...
Abstract—Network-on-chip (NoC) communication fabrics will be increasingly used in many large multico...
Periodic on-chip scan-based tests have to be applied to a many-core processor to improve its dependa...
International audienceThis paper concerns the local and remote use of an Integrated Circuits (IC) Au...
Increasing demand for high quality and reliable operation of the telecommunication network services ...
In this paper, a hardware design of digital systems with remote-diagnostic capability is presented. ...
Design simpli¯cation is becoming necessary to respect the target time-to-market of SoCs, and this go...
Spurred by technology leading to the availability of millions of gates per chip, system-level integr...
This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network ...