Dynamic Replication: The Core of a Truly Non-Intrusive SRAM-based FPGA

The increasing use of reconfigurable computing platforms, employing SRAM-based FPGAs, opens exciting new possibilities since they enable the reutilization of the same hardware resources to implement speed-critical computational tasks, without interrupting system operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of lifetime operation failures, requiring new test / fault-tolerance methods capable of assuring the reliability of the system. Structural concurrent test procedures become particularly important in this context, since it is now possible to replicate and release for test internal FPGA resources, concurrently with — but not affecting — system operation. A new dynamic replication process of active Configurable Logic Blocks (CLBs) is presented in this paper, which enables the implementation of a truly non-intrusive structural concurrent test approach. The experimental results presented prove the effectiveness of this solution. 1