v. PERFORMANCE

As explained in Section III.A, the computations for all rows of the image can be performed in parallel. Thus, the computations for a 512 x 512 image, with 512 processors operating in parallel, can be completed in 512 clock cycles. The critical path consists of an abso-lute difference module followed by a comparator. The Verilog-XL simulation results show that it is possible to operate the implemented circuit with a 1 1 ns clock. Since new inputs can be provided to the system every 11 ns, a 512 x 512 image can be processed in 5.632,US. At 50 frames per second a new pixel value is input to the system every 73.6 ns. Since the minimum clock period is 1 1 ns, this input rate can be handled comfortably, and the entire depth recovery algo-rithm can be run on-the-fly. Better utilization of the performance of-fered by these architectures is possible by interleaving computations for multiple camera sources. By interleaving signals from four cam-era sources and doubling the number of delay stages and registers, the first design for case two can process four independent camera sources simultaneously. The sizes of the row buffers would have to be quadrupled, and rows from four different reference images would be stored in an interleaved fashion. Since high frame rates can easily be supported by the proposed architectures, it is possible to use them for autonomous vehicle navigation applications. Snapshots can be taken frequently and after small camera displacements, leading to re-liable range estimates