TSV Stress Aware Timing Analysis with Applications to 3D-IC Layout Optimization

As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and sil-icon have different coefficients of thermal expansion (CTE), TSV causes silicon deformation due to different tempera-tures at chip manufacturing and operating. The widely used TSV fill material is copper which causes tensile stress on sil-icon near TSV. In this paper, we propose systematic TSV stress aware timing analysis and show how to optimize lay-out for better performance. First, we generate a stress con-tour map with an analytical radial stress model. Then, the tensile stress is converted to hole and electron mobility vari-ations depending on geometric relation between TSVs and transistors. Mobility variation aware cell library and netlist are generated and incorporated in an industrial timing en-gine for 3D-IC timing analysis. It is interesting to observe that rise and fall time react differently to stress and relative locations with respect to TSVs. Overall, TSV stress induced timing variations can be as much as ± 10 % for an individual cell. Thus as an application for layout optimization, we can exploit the stress-induced mobility enhancement to improve timing on critical cells. We show that stress-aware pertur-bation could reduce cell delay by up to 14.0 % and critical path delay by 6.5 % in our test case