Approved by

The integrated circuit scaling has been following the Moore’s Law since 1965 [59, 60, 61]. Within these decades, researchers made great effort to shrink the transistor feature size and maximize the integration level. Together with the growing level of integration, the burden of testing continues to becoming heavier: the number of bits in each test pattern is larger because of increasing number of flip-flops and primary inputs; and larger number of test patterns is required to guarantee fault coverage in a large design. Both factors result in enormous test data volume. Although it is not a problem to generate a big test set by using automatic test pattern generation (ATPG) tools, it puts a higher demand on automatic test equipment (ATE) and prolongs test time, which increase testing cost rapidly. Nowadays, the testing related cost has taken about half of the total manufacturing cost. The industry urges to find a solution. Built-in self-test (BIST) technology is investigated. It’s frequently adopted in some particular cases like memory test to reduce or remove ATE cost. However, for more general testing purpose, BIST technology cannot guarantee fault coverag