Cellular RF transceivers require Si-based

integration of passive components. For RF decoupling application High-Density Trench Capacitors (HiDTC) are mass-manufactured by Philips in a passive integration process with (~25 nF/mm2) capacitors by formation (LPCVD, oxidation) of MOS layers in high aspect ratio macropore arrays in Si [1]. Capacitance enhancement techniqes are known from CMOS technology [2]. Recently, 3D MIM decoupling capacitors integrated in the BiCMOS technology interconnect levels have been reported to have 35 nF/mm capacitance density [3]. In this paper we address the challenges and opportunities in realizing ultrahigh density (>200 nF/mm2) trench capacitors with sufficient breakdown voltage. One emerging technique to accomplish this, is the growth of MIS layer stacks containing so-called high-k dielectrics and metallization layers, grown by Atomic Layer Deposition [4]. However, the application of ALD onto wafers with high aspect ratio trench and pore topography leads to additional challenges: the roughness on the trench sidewalls may cause undesired lower breakdown voltages. Also the formation of interfacial oxide layers (cf. Fig. 1) may lead to undesired lower relative dielectric constants. Furthermore, a proper step coverage and microstructure (morphology and texture) are necessary to achieve good insulating layers, and are certainly not obvious. Adsorption and desorption play an important role in filling and emptying the pores. In particular at the given pressure and macropore dimensions the ALD process proceeds in a different diffusion regime (Knudsen diffusion), limiting the free diffusion of the gaseous ALD reagents and products