This study presents higher order compressors which can be effectively used for high speed multiplications. The proposed compressors offer less delay and area. But the Energy Delay Product (EDP) is slightly higher than lower order compressors. The performance of 8×8, 16×16 and 24×24 multipliers using the proposed higher order compressors has been compared with the same multipliers using lower order compressors and found that the new structures can be used for high speed multiplications. These compressors are simulated with Cadence RTL complier at a temperature of 25°C with the supply voltage of 1.2 V
This paper presents the implementation of a novel high speed low power 15-4 Compressor for high spee...
Abstract: Now a days the technology is growing day by day with faster rate. Particularly the usage o...
Abstract — There is a growing demand for high speed processing and low area design for VLSI and Comm...
For higher order multiplications, a huge number of adders or compressors are to be used to perform t...
Abstract: This article provides an illustration of the design process for 5-2 and 7-2 compressors op...
In this paper, a 8x8 multiplier is realized by using 4-2 and 5-2 compressors. Low-power high speed 4...
Modern technology in the field of VLSI and communication demands for very high-speed processing, lo...
Abstract — In this paper, a novel implementation of 8x8 Multiplier using 4-2 Compressors is presente...
The main objective of this Review is to provide high speed solutions for Very Large Scale Integratio...
At nanometric scales, approximate computing is an attractive prototype used for digital processing. ...
This report presents several classes of XOR and Multiplexor based adders, 4-2 and 5-2 compressors ar...
This paper presents the details of hardware implementation of modified partial product reduction tre...
This paper proposes designs of hierarchy multiplier by utilising different designs on 4:2 and 7:3 co...
With the advent of new technology in the ields of VLSI and communication, there is also an ever grow...
High speed multiplication is one of the critical function in a range of very large scale integration...
This paper presents the implementation of a novel high speed low power 15-4 Compressor for high spee...
Abstract: Now a days the technology is growing day by day with faster rate. Particularly the usage o...
Abstract — There is a growing demand for high speed processing and low area design for VLSI and Comm...
For higher order multiplications, a huge number of adders or compressors are to be used to perform t...
Abstract: This article provides an illustration of the design process for 5-2 and 7-2 compressors op...
In this paper, a 8x8 multiplier is realized by using 4-2 and 5-2 compressors. Low-power high speed 4...
Modern technology in the field of VLSI and communication demands for very high-speed processing, lo...
Abstract — In this paper, a novel implementation of 8x8 Multiplier using 4-2 Compressors is presente...
The main objective of this Review is to provide high speed solutions for Very Large Scale Integratio...
At nanometric scales, approximate computing is an attractive prototype used for digital processing. ...
This report presents several classes of XOR and Multiplexor based adders, 4-2 and 5-2 compressors ar...
This paper presents the details of hardware implementation of modified partial product reduction tre...
This paper proposes designs of hierarchy multiplier by utilising different designs on 4:2 and 7:3 co...
With the advent of new technology in the ields of VLSI and communication, there is also an ever grow...
High speed multiplication is one of the critical function in a range of very large scale integration...
This paper presents the implementation of a novel high speed low power 15-4 Compressor for high spee...
Abstract: Now a days the technology is growing day by day with faster rate. Particularly the usage o...
Abstract — There is a growing demand for high speed processing and low area design for VLSI and Comm...