Parametric reduced order modeling for interconnect analysis

Abstract — VLSI circuit models are subject to pa-rameter variations due to temperature, geometry, pro-cess, and operating conditions. Parameter model or-der reduction is motivated by such practical problems. The purpose is to obtain a parametric reduced order model so that repeated reduction can be avoided. In this paper we propose two techniques: a nominal pro-jection technique and an interpolation technique. The nominal projection technique is effective for small pa-rameter perturbation by using a robust projection. The interpolation technique takes the advantage of simple matrix structure resulting from the PVL al-gorithm. A new moment matching concept in the discrete-time domain is also introduced, which is in-tended for a better performance in waveform match-ing and stability. Interconnect examples are used to test the effectiveness of the proposed methods. I