Abstract—With the reduction in feature size the static power component, such as the leakage power, dominates the dynamic power consumption in the on-chip caches. It has been observed that[2] all cache lines need not be kept active at all times. Only a very few lines during a given window of time need to be actively powered from the footprint, i.e., they are accessed during that time. Earlier research [2] has addressed the issue of how to determine the set of active lines and how long to keep them active (powered). Circuit techniques have also been developed to keep a cache line in low leakage state i.e., Drowsy State when the line is not being accessed or used. Such a cache is called drowsy cache. These circuit techniques try to achieve max...
This paper proposes a combination of circuit and architectural techniques to maximize leakage power ...
International audienceModern processors are using increasingly larger sized on-chip caches. Also, wi...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...
This paper discusses efficient energy saving techniques for on-chip caches, focusing especially on d...
On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature ...
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Alth...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
Technology projections indicate that static power will become a major concern in future generations ...
Power consumption is becoming an increasingly important component of processor design. As technology...
In the design of embedded systems, especially battery-powered systems, it is important to reduce ene...
Power consumption in computing today has lead the industry towards energy efficient computing. As tr...
Recent studies have shown that peripheral circuits, including decoders, wordline drivers, input and ...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
This paper proposes a combination of circuit and architectural techniques to maximize leakage power ...
International audienceModern processors are using increasingly larger sized on-chip caches. Also, wi...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...
This paper discusses efficient energy saving techniques for on-chip caches, focusing especially on d...
On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature ...
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Alth...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
Technology projections indicate that static power will become a major concern in future generations ...
Power consumption is becoming an increasingly important component of processor design. As technology...
In the design of embedded systems, especially battery-powered systems, it is important to reduce ene...
Power consumption in computing today has lead the industry towards energy efficient computing. As tr...
Recent studies have shown that peripheral circuits, including decoders, wordline drivers, input and ...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
This paper proposes a combination of circuit and architectural techniques to maximize leakage power ...
International audienceModern processors are using increasingly larger sized on-chip caches. Also, wi...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...