Efficient Energy Saving Scheme for On-Chip Caches

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Publication date
September 2016

Abstract

Abstract—With the reduction in feature size the static power component, such as the leakage power, dominates the dynamic power consumption in the on-chip caches. It has been observed that[2] all cache lines need not be kept active at all times. Only a very few lines during a given window of time need to be actively powered from the footprint, i.e., they are accessed during that time. Earlier research [2] has addressed the issue of how to determine the set of active lines and how long to keep them active (powered). Circuit techniques have also been developed to keep a cache line in low leakage state i.e., Drowsy State when the line is not being accessed or used. Such a cache is called drowsy cache. These circuit techniques try to achieve max...

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