A background timing-skew calibration technique for time-interleaved analog-to-digital converters

Abstract—This paper presents a background timing-skew cali-bration technique for time-interleaved analog-to-digital converters (ADCs). The timing skew between any two adjacent analog–digital (A/D) channels is detected by counting the number of zero cross-ings of the ADCs input while randomly alternating their sampling sequence. Digitally controlled delay units are adjusted to min-imize the timing skews among the A/D channels caused by the mismatches among the clock routes. The calibration behaviors, including converging speed and timing jitter, are theoretically analyzed and verified with simulations. A 6-bit 16-channel ADC is used as an example. Index Terms—Analog–digital (A/D) conversion, calibration, timing. I