A New Dynamic Bandwidth Re-Allocation Technique in Optically Interconnected High-Performance Computing Systems

As bit rates increase, optical interconnects based high-performance computing (HPC) systems improve per-formance by increasing the available bandwidth (us-ing wavelength-division multiplexing (WDM) and space-division multiplexing (SDM)) and decreasing power dissi-pation as compared to traditional electrical interconnects. While static allocation of wavelengths (channels) in opti-cal interconnects provide every node with equal opportunity for communication, it can lead to network congestion for non-uniform traffic patterns. In this paper, we propose an opto-electronic interconnect for designing a flexible, high-bandwidth, low-latency, dynamically reconfigurable archi-tecture for scalable HPC systems. Reconfigurability is real-ized by monitoring traffic intensities, and implementing dy-namic bandwidth re-allocation (DBR) technique that adapts to changes in communication patterns. We propose a DBR technique- Lock-Step (LS) that balances the load on each communication channel based on past utilization. Sim-ulation results indicate that the reconfigured architecture shows 40 % increased throughput and and 20 % reduced net-work latency as compared to HPC electrical networks. 1