Thickness and Compositional Nonuniformities of Ultrathin Oxides Grown by Rapid Thermal Oxidation of Silicon in

Thin dielectrics grown on 4 in. and 6 in. silicon wafers in a pure N20 ambient using the rapid thermal process (RTP) are non-uniform. For two different flow geometries, the measured thickness of the thin dielectric close to the gas inlet is found to be greater than that found away. The chemical composition of the thin dielectric near the wafer edge is shown to be different han that found near the wafer center. Results of electrical testing across the silicon wafer of metal-oxide-semiconductor (MOS) capaci-tors fabricated with these thin dielectrics are correlated with the chemical composition nonuniformity. The decomposition of N20 may be responsible for the measured thickness and compositional nonuniformities. Thin gate dielectrics grown in a pure N20 ambient on a sili-con substrate using the rapid thermal process (RTP) are a can-didate for submicron CMOS ULSI technology. CMOS ULSI technology requires thin dielectrics on silicon less than 100 A for both p-channel MOSFETs with p § gates and n-channel MOSFETs with n § gates. Boron, which is commonly used to dope polycrystalline silicon for p § gates for surface-channel MOSFETs, can penetrate through thin thermal oxide into th