Reducing Preprocessing Overhead Times in a Reconfigurable Accelerator of Finite Difference Applications

Abstract — Hardware accelerators integrating to general pur-pose processors (GPPs) are increasingly employed to achieve lower power consumption and higher processing speed. However due to impact of memory-wall problem, this kind of acceleration does not always achieve a demanded performance. To resolve this issue, a Large-Scale Reconfigurable Data-Path (LSRDP) has been proposed which is able to reduce the required memory bandwidth. Since the LSRDP consists of a large number of Processing Elements (PEs), it can potentially achieve a very high performance. To take advantages of the LSRDP architecture, a proper implementation for the target application is essential requirement. In this paper, three ways for implementing appli-cations are introduced which include primitive implementation, software optimized version and software optimized with addi-tional memory access controller hardware to decrease the amount of redundant data transfer. Our experimental results reveal about 100 smaller execution time on the LSRDP compared with GPP when the proposed optimization ideas are developed. I