vPROBE:Variation Aware Post-Silicon Power-Performance

Abstract—Variation-aware design involves designing circuits tolerant to process and temperature variations by estimating corner-case scenarios and providing minimum reliability guard bands. In order to extract maximum performance while consuming minimum power, systems need to adapt themselves by making them aware of their composition post-manufacturing. In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance. The proposed scheme is composed of a discretization hardware that exploits the delay/leakage dependence on variability sources characteristic for categorization. We start by analyzing memory structures. The backbone of the binning scheme is the variation-tolerant 3T1D cell which is embedded into existing SRAM circuitry. By measuring the access and retention time of the 3T1D, we show that it is possible to gather sufficient information about the spread of spatial variability. This information can then be used for enforcing circuit-optimizations that are specific to every processor by making them aware of cross-die and intra-die variations. The results of our binning scheme indicate that post-manufacturing nearly 40 % of chips fall into the high-performance low-power bin. However, this can change over the lifetime of the chip owing to constant activity resulting in degradation and performance reduction. To counter the effects of such high and low frequency variations, we also demonstrate the extended capabilities of this scheme in sensing high-frequency temperature variations and adapting to low-frequency changes. Plus, the information gathered by the binning can then provide a platform for cross-layer optimizations. I