On-Chip Ring Network Designs for Hard-Real Time Systems

Rings have been extensively used in high-performance sys-tems to improve performance and scalability, and to reduce cost, energy and design effort. However, in the real-time domain, they have not been thoroughly analyzed to provide worst-case time bounds. We propose several on-chip ring designs in shared-memory multicore processors that enable the computation of trustworthy upper bounds to the time required for a packet to traverse the ring, which is a funda-mental requirement to enable their use in real-time systems. 1