Industrial Evaluation of DRAM Tests

This paper presents the results of 44 well known mem-ory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress combina-tion, and that the theoretically better tests (i.e. those cov-ering more different functional faults) also have a higher fault coverage. However, the currently used fault models still leave much to be explained; e.g., the used data back-grounds and address orders show an unexplainable large variation in fault coverage. 1