tinuous-time – analog–digital converter (ADC) that achieves 57.4-, 51.7-, and 40.2-dB SNR at signal sampling rates of 125, 250, and 500 Ms/s, respectively. The integrated circuit occupied 1.45-mm2 die area, contains 76 transistors, is fabricated in an InP-based HBT technology, and dissipates 1.8 W. We also study the effect of excess delay on modulator performance, and show that excess delay does not affect performance as long as the centroid-in-time of the digital–analog converter pulse remains stationary. Index Terms—Analog-to-digital converter (ADC), continuous time, delta–sigma, HBTs, InP. I
79 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2007.Two integrated circuits using ...
The accuracy of ultra high speed Analog-to-Digital converters (ADCs) decreases at higher input frequ...
Nowadays, the multi-standard wireless receivers and multi-format video processors have created a gre...
Abstract—We report an 18-GHz clock-rate second-order con-tinuous-time – analog–digital converter (A...
Continuous time delta-sigma (CT(Delta-Sigma)) analog-todigital converters (ADCs) are capable of samp...
The trend in modern communications and radar systems is to move the analog-to digital interface as f...
A first-order Delta-Sigma ( ∆Σ ) modulator has been fabricated using a 70GHz (fT) AlInAs/GaInAs-InP ...
Graduation date: 2006In recent years, there has been growing interest in both industry and academia ...
With the unremitting progress in VLSI technology, there is a commensurate increase in performance de...
Compared to SiGe,InP HBTs offer superior electron transport but inferior scaling and parasitic reduc...
This book describes techniques for realizing wide bandwidth (125MHz) over-sampled analog-to-digital ...
Delta-Sigma (ΣΔ) analog-to-digital converters (ADCs) are widely used in wireless transceiver. Recent...
ΣΔ technique has always been the popular choice for designing high resolution data converters due to...
The continuous downscaling of CMOS technology presents advantagesand difficulties for IC design. Whi...
This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at ...
79 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2007.Two integrated circuits using ...
The accuracy of ultra high speed Analog-to-Digital converters (ADCs) decreases at higher input frequ...
Nowadays, the multi-standard wireless receivers and multi-format video processors have created a gre...
Abstract—We report an 18-GHz clock-rate second-order con-tinuous-time – analog–digital converter (A...
Continuous time delta-sigma (CT(Delta-Sigma)) analog-todigital converters (ADCs) are capable of samp...
The trend in modern communications and radar systems is to move the analog-to digital interface as f...
A first-order Delta-Sigma ( ∆Σ ) modulator has been fabricated using a 70GHz (fT) AlInAs/GaInAs-InP ...
Graduation date: 2006In recent years, there has been growing interest in both industry and academia ...
With the unremitting progress in VLSI technology, there is a commensurate increase in performance de...
Compared to SiGe,InP HBTs offer superior electron transport but inferior scaling and parasitic reduc...
This book describes techniques for realizing wide bandwidth (125MHz) over-sampled analog-to-digital ...
Delta-Sigma (ΣΔ) analog-to-digital converters (ADCs) are widely used in wireless transceiver. Recent...
ΣΔ technique has always been the popular choice for designing high resolution data converters due to...
The continuous downscaling of CMOS technology presents advantagesand difficulties for IC design. Whi...
This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at ...
79 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2007.Two integrated circuits using ...
The accuracy of ultra high speed Analog-to-Digital converters (ADCs) decreases at higher input frequ...
Nowadays, the multi-standard wireless receivers and multi-format video processors have created a gre...