A low-power CMOS analog multiplier

Abstract—A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design consid-erations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance, making it very attractive for use in a variety of analog circuits. Index Terms—Analog integrated circuits, analog multipliers, CMOS, low-power design. I