Systematic energy characterization of CMP/SMT processor systems via automated microbenchmarks

Microprocessor-based systems today are composed of multi-core, multi-threaded processors with complex cache hierarchies and gi-gabytes of main memory. Accurate characterization of such a sys-tem, through predictive pre-silicon modeling and/or diagnostic post-silicon measurement based analysis are increasingly cumbersome and error prone. This is especially true of energy-related character-ization studies. In this paper, we take the position that automated micro-benchmarks generated with particular objectives in mind hold the key to obtaining accurate energy-related characterization. As such, we first present a flexible micro-benchmark generation frame-work (MicroProbe) that is used to probe complex multi-core/multi-threaded systems with a variety and range of energy-related queries in mind. We then present experimental results centered around an IBM POWER7 CMP/SMT system to demonstrate how the systemat-ically generated micro-benchmarks can be used to answer three specific queries: (a) How to project application-specific (and if needed, phase-specific) power consumption with component-wise breakdowns? (b) How to measure energy-per-instruction (EPI) val-ues for the target machine? (c) How to bound the worst-case (maxi-mum) power consumption in order to determine safe, but practical (i.e. affordable) packaging or cooling solutions? The solution ap-proaches to the above problems are all new. Hardware measurement based analysis shows superior power projection accuracy (with error margins of less than 2.3 % across SPEC CPU2006) as well as max-power stressing capability (with 10.7 % increase in processor power over the very worst-case power seen during the execution of SPEC CPU2006 applications). 1