Challenges, Trends and Solutions for 3D Interconnects in Lithography and Wafer Level Bonding Techniques

Technology advances such as 3-D Integration are expanding the potential applications of products into mass markets such as consumer electronics. These new technologies are also pushing the envelope of what’s currently possible for many production processes, including lithography processes and wafer bonding. There is still the need to coat, pattern and etch structures. This paper will explore some of the lithographic challenges associated with 3D interconnection technology. Wafer bonding techniques as used in the 3D Packaging will be described with all the challenges and available solutions and trends. Furthermore a new Maskalinger technology will be introduced which allows extreme alignment accuracy assisted by pattern recognition down to 0.25µm. An overall introduction on the challenges, trends and solutions for 3d interconnects in lithography and Wafer Level bonding techniques and the SUSS’s equipment platform will be described accordingly to the needed processes. The processing issues encountered in those techniques will be discussed with a focus on wafer bonding and lithography steps