NOMENCLATURE

Abstract-A physical model considering the effects of grain bound-aries on the turn-on behavior of polysilicon thin-film transistor's (poly-Si TFT's) is presented. Along the channel, the formation of the potential barrier near the grain boundary is proposed to account for the low transconductance and high turn-on voltage of TFT's. The bar-rier height is expressed in terms of channel doping, gate oxide thick-ness, grain size, and external gate as well as drain biases. Drain bias will result in an asymmetric potential barrier and introduce more car-rier injection from the lowered harrier side. It is shown that this con-sideration is very important to characterize the saturation region un-der large drain-bias condition. Based upon the developed potential barrier model, the I-V characteristics are described by the interfacial-layer thermionic-diffusion model. Moreover, thin-film transistors on polycrystalline silicon with a coplanar structure were fabricated for testing. Comparisons between the developed model and the experimen-tal data have been made and excellent agreement has been obtained