Asynchronous Logic Platform with Dynamic Leakage Control using Null Convention Logic

Abstract: Introducing a method of designing an Asynchronous logic platform with dynamic leakage control by finding a fixed threshold that optimizes both performance and static power will become increasingly difficult into the future. Asynchronous machine architecture will be developed and simulated in Verilog HDL, built using gate models derived from an advanced TBSOI process (STMicro, UTSOI, 28nm). The power and performance characteristics of the platform across a number of applications (drawn from the set of streaming signal processing systems relevant to portable and embedded systems) will be explored along with the potential optimizations available to match the platform to the specific workload under consideration