A low-power and bandwidthefficient motion estimation IP core design using binary search

Abstract — A new architecture design for motion estimation using binary matching criterion is proposed to achieve low power and bus bandwidth efficiency. Low power and high bus bandwidth efficiency are the two key issues for portable video applications. To address such issues, we first study an efficient algorithm called all binary motion estimation (ABME), and analyze its architecture issues in operational flow and bus access. Then, we propose an architecture for ABME with four new features: 1) macroblock level pre-processing; 2) efficient binary pyramid search structure; 3) parallel processing of 8 × 8 and 16 × 16 block searches; 4) parallel processing of bi-directional search. Such architecture leads to a superior performance in bus access, speed, and power. Our experiments show that the power consumption is as low as 763μW for IPPPP CIF 30 frames/s and 896μW for IPBPB CIF 30 frames/s. The bus bandwidth savings are 54.3 % for P-frame search and 67.1 % for B-frame search