Strain Engineering and Junction Design for Tunnel Field-Effect Transistor

The tunneling field-effect transistor (TFET) [1]-[18] has attracted attention as a possible alternative to the conventional MOSFET for logic applications at significantly reduced supply voltages and power consumption. Silicon- or silicon-germanium- based TFETs can be easily integrated onto a silicon platform, and may be realized cost-effectively if their performance levels can exceed that of advanced CMOS devices. This motivates the study of performance enhancement for TFETs. In this paper, we discuss technologies aimed at performance enhancement for TFETs, including strain engineering (Fig. 1), source/drain junction profile engineering (Fig. 2), and use of heterojunction materials. Device and circuit simulation results will be discussed as well. Design optimization of multiple-gate TFET devices [7]-[8] will be briefly discussed, including source and drain junction design. The drain junction design affects off-state leakage current Ioff [9] which is related to power consumption, as well as gate-to-drain capacitance Cgd [12] which affects switching speed. The dependence of Cgd on drain design was investigated. The source junction, especially the source dopant profile abruptness, affects the substhreshold swing. We will discuss several ways of controlling the source dopant profile for realizing TFETs with good performance. This includes the use of SiGe/Ge source TFETs for controlling the boron profile, as well as the introduction of additional compensation effects to steepen or sharpen the source dopant profile. In addition, strain engineering of TFETs will be discussed. Mechanical stress was applied to double-gate TFETs to examine the influence of strain on TFET I-V characteristics. It was found that tensile strain increases the drain current while compressive strain reduces the drain current. This is attributed to strain induced band splitting and carrier repopulation, and provide