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gies per nd ing futu elopment of microelectronic ll form sic req circui pmen ollow transi n the lower the efficiency and the yield [3–5]. From the packaging point of view, multi-chips package is the trend of semiconductor industries. Three-dimensional packaging offers a smaller area solution with lower power consumption. Although three-dimensional integration has many advantages, challenges such as reliability, heat dissipation, and testing method-ology are current topics to be solved. This paper reviews and sum-maries wafer-level three-dimensional integrated circuits (3D IC). technologies are the same as those of 3D packaging, this paper will only focus on wafer-level 3D integration. In general, wafer-level 3D integration can be classified into different categories based on the technologies applied. 2.1. Direction of wafer stacking Based on the stacking direction of two device wafers, there are two different kinds of wafer stacking: face-to-face and face-to-⇑ Corresponding author