Add to ORKGAbstract—We propose a surrounding gate MOSFET with vertical channel (SGVC cell) as a 1T DRAM cell. To confirm the memory operation of the SGVC cell, we simulated its memory effect and fabricated the highly scalable SGVC cell. According to simulation and measurement results, the SGVC cell can operate as a 1T DRAM having a sufficiently large sensing margin. Also, due to its vertical channel structure and common source architecture, it can readily be made into a 4F2 cell array. Index Terms—Memory effect, 1T DRAM cell, sensing margin, surrounding gate, vertical channel. I
Abstract—In this article, we evaluated the structural merits and the validity of a partially insulat...
A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage...
One of the major concerns of one-transistor dynamic random access memory (1T-DRAM) is poor retention...
To overcome the scalability issues and process complexity of 1-transistor/1-capacitor DRAM cell, cap...
A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacito...
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a...
Abstract: We fabricated fully depleted (FD) SOI-based 1T-DRAM cells with planar channel or recessed...
The work showcases the utility of core-gate shell-channel (CGSC) architecture for one-transistor dyn...
As the DRAM cell shrinks, the down scaling becomes increasingly difficult in particular due to the c...
A novel 4F(2) dynamic random access memory (DRAM) cell transistor structure was proposed that can so...
Capacitorless dynamic random access memory (DRAM) is a promising solution to cell-area scalability a...
Selected Papers from the Workshop on Frontiers in Electronics 2011 (WOFE-11)San Juan, Puerto-Rico, 1...
International audienceSeveral types of floating-body capacitorless 1T-DRAM memory cells with planar ...
A novel architecture for a vertical MOSFET is proposed and initial investigations conducted by numer...
A new orientation to the conventional MOSFET is proposed. Processing issues, as well as short channe...
Abstract—In this article, we evaluated the structural merits and the validity of a partially insulat...
A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage...
One of the major concerns of one-transistor dynamic random access memory (1T-DRAM) is poor retention...
To overcome the scalability issues and process complexity of 1-transistor/1-capacitor DRAM cell, cap...
A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacito...
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a...
Abstract: We fabricated fully depleted (FD) SOI-based 1T-DRAM cells with planar channel or recessed...
The work showcases the utility of core-gate shell-channel (CGSC) architecture for one-transistor dyn...
As the DRAM cell shrinks, the down scaling becomes increasingly difficult in particular due to the c...
A novel 4F(2) dynamic random access memory (DRAM) cell transistor structure was proposed that can so...
Capacitorless dynamic random access memory (DRAM) is a promising solution to cell-area scalability a...
Selected Papers from the Workshop on Frontiers in Electronics 2011 (WOFE-11)San Juan, Puerto-Rico, 1...
International audienceSeveral types of floating-body capacitorless 1T-DRAM memory cells with planar ...
A novel architecture for a vertical MOSFET is proposed and initial investigations conducted by numer...
A new orientation to the conventional MOSFET is proposed. Processing issues, as well as short channe...
Abstract—In this article, we evaluated the structural merits and the validity of a partially insulat...
A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage...
One of the major concerns of one-transistor dynamic random access memory (1T-DRAM) is poor retention...