Materials and Process Integration Issues in Metal Gate/high-k Stacks and Their Dependence on Device Performance

Electron mobility, work function instabilities and re-growth of the thin SiO2 interfacial layer are main concerns for integrating metal/high-k stacks in high performance CMOS. High electron mobility has been obtained with both high (T~1000 o C) and low (T~400 o C) temperature processing but still the exact mechanism of the metal interaction with the gate stack is not fully understood. Threshold voltage control is also an open issue since metal/high-k stacks exhibit mid-gap work functions after high temperature annealing. Fixes have been proposed which require the introduction of positive (negative) charges near the Si/SiO2 interface to produce devices operating at the Si band edges