A exible heterogeneous multi-core architecture

  • Adrian Cristal
  • Francisco J. Cazorla
  • Daniel A. Jiménez
  • Mateo Valero
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Publication date
January 2007

Abstract

Multi-core processors naturally exploit thread-level par-allelism (TLP). However, extracting instruction-level paral-lelism (ILP) from individual applications or threads is still a challenge as application mixes in this environment are nonuniform. Thus, multi-core processors should be flexi-ble enough to provide high throughput for uniform paral-lel applications as well as high performance for more gen-eral workloads. Heterogeneous architectures are a first step in this direction, but partitioning remains static and only roughly fits application requirements. This paper proposes the Flexible Heterogeneous Mul-tiCore processor (FMC), the first dynamic heterogeneous multi-core architecture capable of reconfiguring itself to fit application re...

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