Abstract—A novel asymmetric MOSFET with no lightly doped drain on the source side is simulated on bulk Si using a device simulator (SILVACO). To overcome the problems of the conven-tional asymmetric process, a novel asymmetric MOSFET using a mesa structure and a sidewall spacer gate is proposed, and it provides a self-alignment process, aggressive scaling, and better uniformity. First of all, we have compared the simulated character-istics of the asymmetric and symmetric MOSFETs. Basically, both asymmetric and symmetric MOSFETs have an n-type channel and the same physical parameters. Compared with the symmetric MOSFET, the asymmetric MOSFET shows better device perfor-mance. Moreover, we have successfully fabricated 50-nm asym-metric NMOSFET...
Double-gate MOSFETs have the most ideal device structure, and are drawing the attentions of research...
This paper investigates the asymmetrical characteristics of junctions and their nearby regions in su...
This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by t...
Ideal MOSFET is intrinsically symmetrical in source and drain, and all existing models describing MO...
Scaling down of the MOSFET has been done extensively to meet the need for high speed devices. Symmet...
An n-channel planar asymmetric Schottky barrier source/drain MOSFET (ASB), in which the source-side ...
A novel field effect transistor (FET), asymmetric gate (AG) FET, is proposed and its excellent perfo...
The spacer technique is proposed for the fabrication of the Asymmetric Schottky Barrier MOSFETs (ASB...
A novel field effect transistor(FET), asymmetric gate(AG) FET,is proposed and its excellent performa...
This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascod...
This paper presents the characterization and simulation results of Lateral Asymmetric Channel (LAC) ...
This paper presents the characterization and simulation results of Lateral Asymmetric Channel (LAC) ...
In this paper, we propose a low-k source side asymmetrical spacer halo-doped nanowire metal oxide se...
A MOSFET semiconductor device having an asymmetric channel region between the source region and the ...
An analytical model is developed for laterally asymmetric channel (graded channel (GQ design in doub...
Double-gate MOSFETs have the most ideal device structure, and are drawing the attentions of research...
This paper investigates the asymmetrical characteristics of junctions and their nearby regions in su...
This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by t...
Ideal MOSFET is intrinsically symmetrical in source and drain, and all existing models describing MO...
Scaling down of the MOSFET has been done extensively to meet the need for high speed devices. Symmet...
An n-channel planar asymmetric Schottky barrier source/drain MOSFET (ASB), in which the source-side ...
A novel field effect transistor (FET), asymmetric gate (AG) FET, is proposed and its excellent perfo...
The spacer technique is proposed for the fabrication of the Asymmetric Schottky Barrier MOSFETs (ASB...
A novel field effect transistor(FET), asymmetric gate(AG) FET,is proposed and its excellent performa...
This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascod...
This paper presents the characterization and simulation results of Lateral Asymmetric Channel (LAC) ...
This paper presents the characterization and simulation results of Lateral Asymmetric Channel (LAC) ...
In this paper, we propose a low-k source side asymmetrical spacer halo-doped nanowire metal oxide se...
A MOSFET semiconductor device having an asymmetric channel region between the source region and the ...
An analytical model is developed for laterally asymmetric channel (graded channel (GQ design in doub...
Double-gate MOSFETs have the most ideal device structure, and are drawing the attentions of research...
This paper investigates the asymmetrical characteristics of junctions and their nearby regions in su...
This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by t...