A controller architecture for high bandwidth active power filter

Abstract—This paper presents a novel architecture for a unit-delay digital deadbeat current controller for a shunt active power filter (APF). The APF is based on a fixed frequency pulsewidth modulated voltage-sourced converter (VSC). The proposed controller increases the APF current-tracking band-width without increasing the VSC switching frequency. Previous APF digital deadbeat controllers have a current-tracking delay of two or more sample-periods. One delay is due to current controller computation, a second sample delay represents VSC actuation time. The paper presents a new controller architecture employing both asynchronous programmable logic and a small microprocessor. Current-tracking feedback control calculations are executed in asynchronous programmable logic to effectively eliminate the controller computation delay. The microprocessor executes fundamental frequency disturbance rejection com-putations and all other supervisory functions. The proposed architecture retains all high-level functions in the microprocessor to minimize controller development time without compromising APF performance. Index Terms—Active filter, current control, deadbeat control, digital control, disturbance rejection, programmable logic, unit-delay, VSC. I