REFERENCES

less than the DICE configuration (hence incurring in a smaller over-head in layout and area). Moreover, the proposed cell has been simu-lated, and assessed for critical charge, power consumption, and delay to overcome the problems encountered in [8]. Using HSPICE, simu-lation results have confirmed that the proposed memory cell accom-plishes the highest soft error tolerance through hardening (it has more than twice the critical charge than the 6T unhardened configuration) and an impressive power-delay product compared with the other hard-ened design commonly referred to as DICE. Therefore, the proposed hardened cell demonstrates superior resistance to soft errors and ex-cellent performance metric as required for high performance memory design. Monte Carlo simulation has confirmed that the soft error hard-ening of the proposed memory cell is accomplished also in the presence of process variations