Population Studies for the Gate Matrix Layout Problem

This paper deals with a Very Large Scale Integrated (VLSI) design problem that belongs to the NP-hard class. The Gate Matrix Layout problem has strong applications on the chip-manufacturing industry. A Memetic Algo-rithm is employed to solve a set of benchmark instances, present in previous works in the literature. Beyond the results found for these instances, another goal of this paper is to study how the performance of the algorithm is affected by the use of multiple populations, together with different individual-migration policies. This comparison has shown to be fruitful, sometimes pro-ducing a strong performance improvement of the multiple populations ap-proaches over the single population ones.