Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Abstract—Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis trans-mitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential inter-connect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with offset reliability at 5 Gb/s. Index Terms—Capacitive pre-emphasis transmitter, glob-ally asynchronous, locally synchronous (GALS), interconnect, low-power design, low-swing, network on chip (NoC), on-chip communication, source synchronous, wave-pipelining. I