A Safe Plating Process for Filling Through Silicon Via over a Novel Cu Electroplating Formula

Three-dimensional (3D) packaging using stacked chip is probably the technology at next generation for IC packaging because it has a promising potential. By the technology we can achieve high silicon efficiency, less signal time delay, less power consumption of system, more speed and clock rate due to lower overall interconnection … etc. For example, an 80-core processor in computer system and dozens of gigabyte memory may accordingly come true in the next generation. For manufacturing 3D packaging of IC chip, through silicon vias (TSV) plays an important role for connecting each chip in z-direction. The fabrication processes of TSV include etching, CVD, PVD, cupper plating, CMP, polishing, and back surface bump formation. The highest process cost is cupper plating. It results from lon