Abstract — While numerous prior studies focused on perfor-mance and energy optimizations for caches, their interactions have received much less attention. This paper studies this inter-action and demonstrates how performance and energy optimiza-tions can affect each other. More importantly, we propose three optimization schemes that turn off cache lines in a prefetching-sensitive manner. These schemes treat prefetched cache lines dif-ferently from the lines brought to the cache in a normal way (i.e., through a load operation) in turning off the cache lines. Our experiments with applications from the SPEC2000 suite indicate that the proposed approaches save significant leakage energy with very small degradation on performance. I
As data prefetching is used in embedded processors, it is crucial to reduce the wasted energy for im...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching of...
The line size/performance trade-offs in off-chip second-level caches in light of energy-efficiency a...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
One of the significant issues of processor architectureis to overcome memory latency. Prefetching ca...
Abstract—With the reduction in feature size the static power component, such as the leakage power, d...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
As the trends of process scaling make memory system even more crucial bottleneck, the importance of ...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
Abstract—Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadverten...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
There has been intensive research on data prefetching focusing on performance improvement, however, ...
Processor performance has increased far faster than memories have been able to keep up with, forcing...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
As data prefetching is used in embedded processors, it is crucial to reduce the wasted energy for im...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching of...
The line size/performance trade-offs in off-chip second-level caches in light of energy-efficiency a...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
One of the significant issues of processor architectureis to overcome memory latency. Prefetching ca...
Abstract—With the reduction in feature size the static power component, such as the leakage power, d...
Power dissipation is increasingly important in CPUs rang-ing from those intended for mobile use, all...
As the trends of process scaling make memory system even more crucial bottleneck, the importance of ...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
Abstract—Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadverten...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
There has been intensive research on data prefetching focusing on performance improvement, however, ...
Processor performance has increased far faster than memories have been able to keep up with, forcing...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
As data prefetching is used in embedded processors, it is crucial to reduce the wasted energy for im...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching of...