Impact of parameter variations on multicore chips

Increasing variability during manufacturing and during runtime are projected for future generation microprocessors. This paper intro-duces a pre-RTL, architectural modeling methodology that incor-porates the impact of manufacturing and runtime temperature vari-ations on delay and power for both combinational logic and SRAM structures. The model is then used to show that frequency varia-tions among microarchitectural functional units and among cores are relatively small in a high-performance microprocessor design. However, the impact of within-die systematic process variations on leakage power will result in major leakage variation across multiple cores on a single chip. WID leakage variation can cause core-to-core leakage to differ by as much as 45%