Parallel Simulation of SystemC TLM 2.0 Compliant MPSoC on SMP Workstations

The simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). The SystemC TLM2.0 (Transaction Level Modeling) approach accelerates the simulation by using Interface Method Calls (IMC) to implement the communications between hardware compo-nents. Another source of speedup can be exploited by par-allel simulation. Multi-core workstations are becoming the mainstream, and SMP workstations will soon contain sev-eral tens of cores. The standard SystemC simulation engine uses a centralized scheduler, that is clearly the bottleneck for a parallel simulation. This paper has two main contri-butions. The first is a general modeling strategy for shared memory MPSoCs, called TLM-DT (Transaction Level Mod-eling with Distributed Time). The second is a truly parallel simulation engine, called SystemC-SMP. First experimental results on a 40 processor MPSoC virtual prototype running on a dual-core workstation demonstrate a 1.8 speedup, ver-sus a sequential simulation