Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs

Abstract—This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this case, coherence must be enforced in all situations and specially when a line is turned off to save power. In particular, we introduce three techniques: the first one turns off the cache lines by using the coherence protocol invalidations, the second one is an implementation of a cache decay technique specific for coherent caches, the third one is a performance-optimized decay-based technique for coherent caches. Experimental results, carried out by using accurate performance/thermal/energy models, show that appreciable power savings can be achieved by properly designing a leakage optimization technique. We target a CMP composed of 4 cores and 1 to 8 MB of total cache. For 4MB, the proposed techniques show a 13%, 30%, and 21 % energy reduction, respectively, at the cost of 0%, 8%, and 2 % performance loss. For other cache sizes the behavior is qualitatively similar. Keywords-leakage; chip multiprocessor; CMP; Multicore; Cache Decay; Coherence; I