Resource augmentation for fault-tolerance feasibility of real-time tasks under error bursts

Dependability is a vital system requirement, particularly in safety critical and mission critical real-time systems, due to the potentially catastrophic consequences of failures. In most critical applications different fault tolerance mecha-nisms using redundancy are employed to prevent possible failures. In the case of real-time systems the system de-signer must ensure that the task set is feasible even under faults, which we refer to as ’fault tolerance feasibility’. Due to cost considerations, often temporal redundancy has been prevalently used to meet this objective. In this paper we focus on guaranteeing fault-tolerance fea-sibility under error bursts on uni-processor systems by the usage of resource augmentation, specifically through proces-sor speed-up. Firstly, we derive a processor demand bound based sufficient condition for a set of real-time tasks to be fault tolerance feasible under an assumption that no more than one error burst occurs during the hyper-period of the task set. Subsequently, we derive the necessary resource augmentation bounds (i.e., the processor speed-up), that guarantees the fault tolerance feasibility, if the sufficient test fails. Finally, we prove that, if the error burst length is no more than half the shortest relative deadline of the task set, the minimum processor speed-up required to guarantee fault tolerance feasibility is upper-bounded by 6